To enable the advancement of Si based technology, necessary to increase computing power and the manufacture of more compact circuits, significant changes to the current planar transistor are a necessity. Novel transistor architectures and materials are currently being researched vigorously. This thesis, on the electrical characterisation of non-standard orientated MOSFETs and multi-gate transistors displays detailed insight into the carrier transport and resulting performance limiting mechanisms. The results are composed of three parts. Firstly, the standard method of extracting carrier effective mobility from electrical measurements on MOSFETs is reviewed and the assumptions implicit in this method are discussed. A novel technique is suggested that corrects the difference in drain bias during current-voltage and capacitance-voltage measurements. It is further shown that the lateral field and diffusion corrections, which are commonly neglected, in fact cancel each other. The efficacy of the proposed technique is demonstrated by application to data measured on a quasi-planar SOI finFET at 300 K and 4 K. The second part is based on the electrical characterisation of n+poly-Si/SiO2/Si nand p- MOSFETs fabricated on (100) and (110) substrate orientations with the full range of channel directions. In depth analysis of the electron and hole mobility was performed at 300 K and 4 K. The 4 K mobilities were modelled in terms of ionised dopant impurity, local SiO2/Si interface charge and roughness scattering mechanisms. RMS (root mean squared) roughness values in the range 0.34 − 0.38nm and correlation lengths of 2.0 − 2.3 nm were extracted revealing comparable interface quality between the (100) and (110) surfaces. The third part examines the electrical characterisation of TiN/HfSiO2/Si n- and pfinFETs. Fin top surface and sidewalls are in the (100) and (110) planes respectively. Fins have a height of 65 nm with widths in the range of 1872 nm (quasi-planar) to 12 nm. Detailed analysis revealed vertical compressive strain induced by the gate into the fin sidewalls, which enhanced the electron mobility by 60% above the (110) reference, whilst leaving the hole mobility unaffected. Qualitative analysis of the 4 K mobilities suggests that roughness is higher on the sidewalls than on the top surface. This was attributed to the damage caused by the dry etch, used to pattern the fins. A model for remote charge scattering at the HfSiO2/SiO2 interface was developed. 4 K mobilities from the quasi-planar n- and pfinFETs were then modelled in terms of remote charge, ionised dopant impurity, local SiO2/Si interface charge and roughness scattering mechanisms. Remote charge densities of 8x1012 cm-2 were subsequently extracted. Scattering from these charges was shown to be the dominant scattering mechanism in the quasi-planar n-finFET mobility at 300 K.