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Title: An on-board real-time image compression system for Earth Observation satellites
Author: Yu, Guoxia
ISNI:       0000 0004 2681 2250
Awarding Body: University of Surrey
Current Institution: University of Surrey
Date of Award: 2009
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Improvements on imaging resolutions of Earth Observation satellites have dramatically increased the volume of the captured imaging data. To mitigate the limited on-board data memory and transmission bandwidth, on-board image compression becomes the most critical requirement. A comprehensive survey of on-board image compression systems is presented, including their algorithms and implementations, followed by analysis and development trends. Based on this, a new architecture of an on-board real-time compression system is proposed. The architecture features intelligent pre-processings and different types of compression. The Brightness Difference Compensation (BDC) technique brings significant improvements to both lossless and lossy compression. The gradient image based phase correlation (GradPC) inter-band registration technique is very accurate and more robust reducing the failure rate from 44% down to 13%. The failure detection mechanism of GradPC can also function as a simple two-type classifier. A new efficient lossless image compression scheme is proposed. An embedded BDC technique is introduced which is less complex but achieves comparable performance to BDC. The new V-scan facilitates the advantages of both multidimensional prediction and independent coding on a small region. The introducing of spectral gradient enables an efficient switching between intra-band coding and inter-band coding mode of the multidimensional predictor. The nearly constant compression performance on the varying size of independent coding region brings high error-resilience ability on the small size end. A new configurable high-level hardware-accelerator model is able to generate the most efficient hardware implementation for a particular application scenario. Two new algorithmic optimization techniques - supreme quantization and multiplier-free, are applied to this model, which reduce implementation resources and power consumption. A fully pipelined design achieves real-time processing ability with a throughput of more than 150 Msamples/second. A reconfigurable LEON3-based System-on-Chip (SoC) platform is proposed for imaging payload control and data processing, featuring reconfigurability, high flexibility and redundancy. The developed lossless compression core is integrated as a hardware accelerator in the SoC. Two demonstration systems provide a proof of correctness for the compression operation and the realtime compression capability of the SoC.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available