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Title: Investigating the Scalability of Tiled Chip Multiprocessors using Multiple Networks
Author: Preethi, Sam
ISNI:       0000 0001 3498 9687
Awarding Body: The University of Manchester
Current Institution: University of Manchester
Date of Award: 2009
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The era of billion and more transistors on a single silicon chip has already begun and this has changed the direction of future computing towards building chip multiprocessors (CMP) systems. Nevertheless the challenges of maintaining cache coherency as well providing scalability on CMPs is still in its initial stages of development. This thesis therefore investigates the scalability of cache coherent CMP systems.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available