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Title: Domain specific reconfigurable architectures for image and video processing applications
Author: Pai, Arjun Kasturi
ISNI:       0000 0001 3463 9505
Current Institution: Queen's University Belfast
Date of Award: 2007
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Current approaches towards building a reconfigurable processor are targeted towards general purpose computing or a limited range of media specific applications and are not specifically tuned for mobile multimedia applications. The complexity, real-time constraints and cost efficient implementations of future multimedia systems need to be addressed early in the design lifecycle. Besides, the increasing demand for mobile multimedia processing with stringent performance constraints for reduced power, lower chip area and high flexibility naturally demand an architecture tailored specifically for low power image and video processing applications. The research undertaken and presented in this thes~s is targeted towards developing a powerefficient reconfigurable silicon core s~itable for integration within a System-on-aChip (SoC) design framework. A reusable cluster based approach was employed to identify specific sequences of operations that can be implemented and accelerated using reconfigurable hardware. A strong focus of this work is on image transformations and video processing which tends to dominate computational requirements involving up to two-thirds of computational complexity of a video or image encoder. A set of application benchmarks (discrete cosine transform, discrete wavelet transform and motion estimation) were used as case studies to demonstrate the computational efficiency and flexibility of the proposed domain-specific reconfigurable architecture (DSRA) presented in this thesis. These case studies were validated, evaluated and compared in . terms of their performance cost metrics namely speed, silicon area and dynamic power consumption. A key feature of the proposed architecture is its capability to cater to a range of existing benchmark architectures by reconfiguring them to suit a broad range of specifications. This work demonstrates and quantifies that a domainspecific reconfigurable approach provides a middle-ground between standard cell ASIC design and SRAM programmable FPGA implementation.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available