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Title: Memory-centric system level design of heterogeneous embedded DSP systems
Author: Fischaber, Scott Johan
ISNI:       0000 0001 3465 5679
Awarding Body: Queen's University of Belfast
Current Institution: Queen's University Belfast
Date of Award: 2008
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Modern embedded systems for DSP applications are increasingly being implemented on heterogeneous processing architectures, consisting of multiple processors and programmable hardware such as FPGAs. The layered memory structure of FPGAs provides an open platform for memory organisation which many algorithms can benefit from. To efficiently target these platforms, high level design tools are being developed to target these architectures; often for DSP applications, these tools have been based around process networks, and as such, their memory architectures typically closely match the simple FIFO buffering employed by these models. This is not always ideal in a hardware implementation, where off-chip memory accesses may be required, particularly when there is data reuse inherent to the algorithm. This thesis proposes a formalised methodology to synthesise efficient memory architectures for FPGA-based DSP systems from a high level dataflow model. This includes reducing the memory requirements of the system through transformations, model refinements and by including the hardware characteristics into the dataflow analysis: Standard dataflow transformations have been characterised so that their effects on the memory subsystem are apparent and these transformations have been placed appropriately in a memory-centric design flow. The memory generation techniques for hardware cores on these FPGA platforms are also analysed, providing extensions which can reduce memory requirements through automatic sub-scheduling using a range of MoCs. These techniques effectively target the distributed nature of FPGA memories to introduce memory hierarchies into the implementations, targeting any data reuse inherent to the application which can take advantage of the memory architecture. This layered memory approach is used to reduce the number of accesses reqUired to large memories, which in turn can increase performance and reduce power consumption. For a motion estimation algorithm the reqUired bandwidth for off-chip memory accesses can vary by a factor of a thousand between two DFGs. For a 2-D convolution algorithm, the total reqUired memory is reduced by half though refinement of the system level model. This methodology has been demonstrated in the design of a video encoder and template matching algorithm and used to efficiently implement the memory sub-systems.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available