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Title: Reconfigurable SoC architectures for video motion compensation
Author: Lü, Liang.
ISNI:       0000 0001 3614 2463
Awarding Body: Queen's University of Belfast
Current Institution: Queen's University Belfast
Date of Award: 2008
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Research has been undertaken into domain-specific reconfigurable architectures for future System-on-Chip applications. In particular the focus has been on video compression systems with the objective o£developing systems suitable for most of the common video compression standards. An important aspect of the research presented is a new domain-specific architecture for real-time integer motion estimation (ME). This has been derived from a detailed investigation of the properties of custom ME architectures, with sharable and non-sharable sub-functions multiplexed onto a reconfigurable data-path which is programmable via data configuration lines. Design studies demonstrate that this architecture requires only slightly more power and silicon area to achieve a high degree of flexibility when compared with equivalent dedicated circuits. It also saves at least an order of magnitude of power consumption compared with an equivalent FPGA implementation. The architecture also provides higher throughput rates and smaller silicon area compared with the best dedicated designs to date for H.264 and AVS. This thesis also describes a new domain-specific reconfigurable sub-pixel interpolation architecture for multi-standard video coding systems. Flexibility has been achieved by using a: multiplexed reconfigurable data-path that allows the choice of different filter coefficients corresponding to different video standards. A detailed design study shows that this requires only a 6.6% overhead to cater for the most complex scenario - MPEG-4. Finally, a new real-time architecture for rate-distortion optimisation for detennining the best matching motion vector is proposed. In traditional methods, this is derived from a pre-defined look-up table whose size is inflexible once fabricated. The proposed real-time architecture calculates the value of this cost function. The design studies show that this approach saves approximately 26% of the silicon area when compared with the smallest look-up table implementations reported to date. Moreover, it is easily extended to larger motion search range with little increase in silicon area.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available