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Title: An SOPC Based Image Processing System
Author: Wu, Fan
ISNI:       0000 0001 3573 2867
Awarding Body: University of Liverpool
Current Institution: University of Liverpool
Date of Award: 2007
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Recent advances in semiconductor technology have made it possible to integrate an entire system including processors, memory and other system units into a single programmable chip - FPGA, these configurations are called 'System-on-aProgrammable- Chip' (SOPC). SOPCs have the advantage that they can be designed quicker than existing technologies and are cheap to produce for low volume «10,000) applications. Also, SOPCs are of great benefit as they offer compact and flexible system designs due to their reconfigurable nature and high integration of features. One processor intensive application, which is ideal for SOPC technology, is that of image processing where there is a repeated application of operations on the 2D data. This research investigated the use of SOPC technology for image processing by developing a modular system capable ofreal-time video acquisition, processing and display. An sope Based Image Processing System Abstract Abstract This system is comprised of a CameraLink CMOS camera with a custom designed camera interface card for video acquisition, a VGA mode CRT monitor with a Lancelot VGA card for video display, an industrial SDRAM device for video data buffering, and an Altera Apex 20K FPGA for evaluating the SOPC design. Four custom designed IP components have been developed and integrated with other Altera provided standard IP components to drive all off-chip peripherals and perform the required video functions such as processing the images. These custom designed IPs are the video capture controller, video display controller, video memory controller and Cache. A Nios processor was chosen to perform the actual image processing, and the whole system was developed on the Altera Nios development board. In order to solve the complex on-chip data communication, while not degrading the transferring speed of largeamounts of video data, an effective solution called Simultaneously Multi-Mastering Avalon Streaming Transfer with Peripheral-Controlled Waitrequest was raised. Rather than using the software approach to initialise DMA-like transfers, this solution takes advantage of the FPGA hardware resource to perform bus arbitration and hence increases the system efficiency. The system produced is an alternative to conventional desktop-based, i.e. a visionbased closed loop process control system for weiding, or microprocessor-based vision systems. September 2007 FanWu Supplied by The British Library - 'The world's knowledge'
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available