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Title: Integration of high-K gate dielectrics in silicon based semiconductor technology
Author: Poolamai, Nipapan
ISNI:       0000 0001 3494 4411
Awarding Body: Newcastle University
Current Institution: University of Newcastle upon Tyne
Date of Award: 2005
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To integrate high-K gate dielectrics into metal-oxide-semiconductor field-effect transistors (MOSFETs), challenges arise due to properties of high-K gate dielectrics themselves. High temperature processes after the formation of high- K gate dielectrics have been a major concern. Investigations on process sequences of MOSFETs with high-K gate dielectrics have been carried out and a MOSFET process flow with reduced thermal budget has been proposed. Furthermore, the application of high-K gate dielectrics to silicon carbide (SiC) tech.,.'1ology has been proposed recently due to the inferior Si02/SiC interface quality and reliability problems of SiC MOS power devices. Therefore, a high-Kgate stack structure on SiC has also been investigated. The effects of process sequences in conventional and replacement gate process on device characteristics of 70-nm MOSFETs with different high-K gate dielectric constant were studied by using process and device simulation, SILVACO TCAD software. It was found that high-K MOSFETs created by replacement gate process have a degradation in short channel performance whilst less short-chi:mnel effects are found in high-K MOSFETs created by conventional process. In addition, the use of high-K dielectrics in MOSFETs affects DC characteristics and gate delay of circuit performfu''1ce. However, with different process sequences, the device and circuit performance exhibited differing effects. This may be due to the changes of the doping and profile in the silicon substrate implicit in the fabrication sequences, and optimised retrograde channel doping profile may help to improve device performance of high-K devices. The PMOS process flow with reduced thermal budget was proposed to fabricate Ti02/Si02 Si MOSFETs with the gate lengths of 1, 3, 5, 10, 100 and 200 /lm. The capacitance-voltage characteristics were well behaved. The capacitive effective thickness (CET) of Ti02/SiOz gate stacked film was about 30-35 nm and its dielectric constant was ~ 14. Negative fixed oxide charges of 1.2x 1all cm-z, the frequency dispersion, and hysteresis were observed. The interface trap density (Dit) was about 1.1xl011 cm-2eV-! near midgap. The breakdown field. was 8 MV/cm. For the transistor performance, the short-channel effects were found. Since PMOS process flow with reduced thermal budget was introduced, the oxide quality found in TiOzlSiOz PMOS tra.l.'1sistors have approximately the same quality as that in TiOz/SiOz capacitors. The TiOz/Si02 gate stack structure was also proposed in 4H-SiC MOS capacitors. L11 this study, the oxidation temperature of evaporated titanium films was varied. From the experiment, the oxidation temperature of 800 °C provided good electrical characteristics. It gave CET of 17 TIm. The negative oxide trap charges were 2.87xl012 q(C/cmz) ai1.d interface trapped densities were 2-3x 012 cm-2 eyl at Ec-ET = 0-0.32 eV. The current density at gate voltage of 1 V was 2.4 X10-6 Ncmz. The use of SiOz films as an interfacial layer helps to improve leakage current of devices.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available