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Title: The management of dynamically reconfigurable computing systems
Author: Su, Lan
ISNI:       0000 0001 3488 8819
Awarding Body: University of Manchester
Current Institution: University of Manchester
Date of Award: 2008
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An abstract of the thesis of Lan Su submitted to The University of Manchester Faculty of Engineering for the degree of Doctor of Philosophy of Engineering presented March 2008. Title: The management of Dynamically Reconfigurable Computing Systems In recent years, there has been significant interest in the use of reconfigurable computing devices such as Field-Programmable Gate Array (FPGA) to accelerate software computation. Many contemporary FPGAs support the ability to reconfigure some, or all, of the user logic !f run-time, Le. during the operation of the system. This is known as dynamic reconfiguration. One advantage of dynamic reconfiguration is the ability to execute designs that require a larger number of gates than are present on the FPGA. Some SRAM-based FPGAs support dynamic partial reconfiguration, which enables part of an FPGA to be reconfigured the rest continues to operate. Such a capability opens up the prospect of multitasking hardware, analogous to the execution of concurrent software processes by an operating system. This thesis discusses the development of a multi-tasking operating system which supports the execution of applications by configuring the FPGA resources to execute hardware tasks at run-time. The operating system is called the FPGA Support System (FSS). This runs on a conventional processor attached to the target FPGA. For pragmatic reasons, the FSS was implemented on a personal computer, and the FPGA was a widely used XililLX Virtex device on a PCI card. The key contribution of this thesis is the development of a device driver for the FSS, which can manipulate the Virtex bitstream at run-time to achieve partial reconfiguration. Due to the fact that the architecture of the Virtex is frame-based (or colum.n.-based), two configuration algorithms (simple and advanced) were developed to support 'system calls' for task creation, deletion, suspension, resumption, etc, and all of these facilities are demonstrated via application programs. The experimental results indicated that the simple approach, suitable for one-dimensional column-based task placement, was an order of magnitude faster than the advanced method that can support two-dimensional placement. Research into hardware task scheduling and placement was also carried out. FSS algorithms were developed to decide when and where to place waiting tasks, aild to reuse hardware area occupied by terminated tasks as frequently as possible, thus would be executing the greatest number of tasks on the hardware as more as possible and achieving greater hardware resource utilisation. The management of dynamic reconfiguration for both 1D and a simplified form of2D placement (quasi2D) were simulated and compared using different scheduling policies. These simulation results indicated that a hybrid policy based upon the two scheduling policies provided the best results, and the quasi-2D task placement algoritr.J:11 performed better than 1D placement algorithm in the terms of average utilisation. Supplied by The British Library - 'The world's knowledge'
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available