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Title: Development of A1GaN/GaN HBTs and HFETs for high power and high frequency operation
Author: Green, Robert Terence
ISNI:       0000 0001 3517 4201
Awarding Body: University of Sheffield
Current Institution: University of Sheffield
Date of Award: 2008
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GaN-based semiconductors show promise for the fabrication of electronic components capable of high power, high frequency operation. This has lead to the development of both AlGaN/GaN heterostructure field effect and bipolar junction transistors. In order to increase the efficiency of these devices novel fabrication technologies are examined. Contact resistances to buried p-type layers, exposed using a novel wet etch, were found to be superior when compared to those formed on dry etched structures. Utilising this technology in conjunction with a novel inverted n-p-n AlGaN/GaN HBT is found to increase the emitter-base heterojunction quality and also reduces growth complexity. Replacing the n-type collector with a Schottky diode was found to significantly reduce leakage in the component and enable normal operation under common emitter bias conditions. Bulk and surface trapping effects in AIGaN/GaN heterostructures are independently identified. Bulk traps are found to be located close to or at the me~-semiconductor interface which results in a modification to the HFET band structure. Gate leakage current along the AIGaN surface is found to be controlled by injection from the gate and a surface hopping conduction mechanism which dominates at high and low temperature respectively. Passivation of the structure using SiN reduces current flow at the AIGaN surface. Employing a plasma pre-treatment, contamination at the surface of the device can be removed allowing intimate contact between the passivation and AlGaN films. Using a CF4 plasma treatment is found to remove these contaminants and deposits a thin film of AlF3 on the AlGaN surface which reduces current collapse in AlGaN/GaN HFETs to negligible levels. GaN capping layers on HFETs can reduce both parasitic contact resistances and also reduce current collapse. Methods of selectively etching through the GaN capping layer are presented in order to develop a suitable self-aligned gate recess process.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available