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Title: Self Testing Asynchronous Processors for Fixed Point and Logarithmic Number Systems
Author: Marshall, Matthew John
ISNI:       0000 0001 3619 7106
Awarding Body: Newcastle University
Current Institution: University of Newcastle upon Tyne
Date of Award: 2008
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As a result of advances in technology shrinking device dimensions, the occurrence of transient errors is increasing. This together with the concomitant reduction in supply voltages has decreased noise margins causing system reliability to be reduced, at a time when electronic systems are being used increasingly in 'safety critical' applications. In a world where power and heat have become a serious factor when deciding upon a particular processor, system performance still remains dominant. However, simply increasing clock speeds has proven to be limiting to designers and alternate ways to improve performance have been investigated. Improvements have been realised using different number formats to simplify calculations and by using multi processor/core systems. Distributed computing has led to increased performance by increasing the number of physical processors (or cores) whilst still utilising a single high speed clock source. The distribution of high frequency clocks across larger and larger'ateas requires highly tuned distribution networks to reduce 'clock skew' issues and results in large overheads in power and area. Multiple clocks can be used to separate functional units with some form of communication between them, possibly using asynchronous methodology; this is known as Globally Asynchronous Locally Synchronous (GALS). Unlike synchronous systems which use discrete time, the remaining method uses continuous time to provide a fully asynchronous operation where no clock exists and systems operate using handshake communication. Asynchronous systems offer lower power due to reduced switching and natural sleep modes, as well as the possibility for simplified 'functional block' replacements and upgrades. This thesis examines the design and implementation of a serIes of comparable processors using synchronous and asynchronous design styles with and without Concurrent Error Detection (CED) abilities and using fixed point and logarithmic number systems. The CED scheme utilises the information redundant code, Dong's Code, which is a variant of the Berger Code. The designs are targeted to ASIC and FPGA implementation with the FPGA designs produced with a logic gate equivalence to that of the ASIC. The work also provides evidence that asynchronous technology can provide much improved power efficiency (up to 22%) at a time when power savings in the microelectronic designs are becoming critical to improved sales performances and customer choice. Furthermore, it has been shown that the power overhead for the asynchronous CED processors were 5% less than that of the synchronous processor without CED. The reduced power consumption of the asynchronous circuits coupled with area savings of up to 8% makes asynchronous design both attractive and viable for reliable computation. To the best of the author's knowledge, the description of the design of the Asynchronous Logarithmic Processor with CED has not been, to date, reported in open literature.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available