Use this URL to cite or link to this record in EThOS: | https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.486189 |
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Title: | Debug Support Strategy for System-an-Chips with Multiple Processor Cores | ||||
Author: | Hopkins, Andrew B. T. |
ISNI:
0000 0001 3581 4758
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Awarding Body: | University of Essex | ||||
Current Institution: | The University of Essex pre-October 2008 | ||||
Date of Award: | 2008 | ||||
Availability of Full Text: |
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Abstract: | |||||
Increased integration has resulted in the creation of so called System-onChip
(SoC) devices. They ~embed all the essential parts of an advanced computer
into a single silicon chip in order to achieve compactness, reduced material
cost, higher performance and lower power consumption. An adverse
consequence of this integration is that the external interfaces once observed
dUring debugging are now inaccessible within the chip, no longer aiding
development. Debug support brings back this otherwise lost visibility by
providing an observation window into the SoC, the heart of the overall system.
Integration now enables SoCs to contain more than one processor core. which
has made existing debug support strategies ineffective at supporting
application development. Moreover. these existing single processor oriented
debugging strategies fail to align with the circuit reuse based methodologies
necessary to rapidly_ create new SoCs.This thesis presents a novel debugging strategy that fully encompasses the
requirements of SoC creation and application development. The strategy
enables realisation of advanced embedded systems that incorporate complex
SoCs; devices containing multiple processor cores and other active cores. It
achieves these advantages through a package of novel contributions.
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Supervisor: | Not available | Sponsor: | Not available | ||
Qualification Name: | Thesis (Ph.D.) | Qualification Level: | Doctoral | ||
EThOS ID: | uk.bl.ethos.486189 | DOI: | Not available | ||
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