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Title: Modelling for Strained Silicon CMOS Technology
Author: Tsang, Yuk Lun
ISNI:       0000 0001 3537 0624
Awarding Body: Newcastle University
Current Institution: University of Newcastle upon Tyne
Date of Award: 2008
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The metal-oxide-semiconductor field effect transistor (MOSFET) has been scaling down aggressively over many technology nodes in order to follow Moore's Law predictions. Strain engineering to the device channel can modify the band structure and so enhance carrier mobility. It has widely been incorporated to improve device performance. Novel modelling techniques, including strain effects, are necessarily required. The electrical characteristics of semiconductor hav9r.their origin in energy band structure. In this thesis, a new semi-analytical model is developed lor describing the energy band structure under strain conditions. Furthermore, the band parameters of the SiGe heterojunction are generalised for different combinations of Ge fractions. Those results can be used to understand and to model the transport properties of carriers and the variation of threshold voltage measured from strained Si MOSFETs. The calculated band parameters are then entered into a newly developed model to calculate the threshold voltage variation in strained Si MOSFETs having a dual channel architecture. Finally, understanding the strain effects on the band structure is extended to the modelling of strained-induced variation of carrier mobility using the piezoresistance concept. The overviews of each main-result chapter in this thesis are given below: In Chapter 3, model using the original k'p method for the energy dispersion of holes in the inversion layer of p-MOSFETs is complicated and demands extensive computational resource. Those are the reasons why the development of simulations for p-MOSFETs lagged behind their n-MOSFET counterpart. In this work, the band structure for holes in an inversion layer is dramatically simplified using a new semi-analytical model. It is described by novel non-parabolic and anisotropic expressions such that the overall computational complexity is significantly reduced compared to a fully numerical treatment. Here, the band parameters are also generalised for different Ge fractions in a SiJ-xGexfilm grown on a relaxed SiJ.yGeyvirtual substrate. In Chapter 4, an analytical model of threshold voltage for globally strained SiiSiGe CMOS devices using a dual channel architecture is developed. A model to calculate threshold voltage is developed which includes effects of device geometry, material properties, such as band parameters and permittivity, and channel and substrate doping concentrations. The threshold voltage roll-off due to short channel effects is included using the voltage-doping transformation. The proposed model is validated in agreement with simulations and experiments. It provides a physical insight for the variation of threshold voltage for both n- and p-MOSFETs having a dual channel architecture and it can be generalised to apply to single channel devices also. In Chapter 5, the conventional piezoresistance model has commonly been used to describe mobility enhancement for low levels of process induced strain in CMOS technology. However, many reports show it failing at the high levels of stress needed for future technology generations. This is because approximations made are only valid for very low stress levels. The piezomobility formulation removes an approximation assumed in the commonly-used piezoresistance model and improves its accuracy to much higher stress regimes while retaining its simplicity. The validity of the new formulation is demonstrated for Monte Carlo simulations of mobility, nMOSFETs, pMOSFETs, and nanowires in stress regimes where the commonly-used piezoresistance model has previously been reported to fail.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available