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Title: Material characterisation of strained Si/SiGe MOSFET devices
Author: Escobedo-Cousin, Enrique
ISNI:       0000 0001 3449 1256
Awarding Body: Newcastle University
Current Institution: University of Newcastle upon Tyne
Date of Award: 2008
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In this study, material investigations of strained Si/SiGe platforms for MOSFET applications are presented. The device performance advantages of introducing strain in the MOSFET channel have become well established in recent years. Biaxial strain changes carrier mobility by altering the band structure of the channel, leading to a reduction in carrier effective mass and the time between scattering events. Electron mobility benefits from the tensile strain achieved by the epitaxial growth of Si on a strain-relaxed SiGe buffer (SRB). Since holes, in contrast, benefit from compressive strein, dual-channel architectures comprising a compressively strained SiGe layer beneath a tensely strained Si surface channel have been proposed for CMOS applications. However, dual-channel nMOSFETs consistently exhibit lower performance than those fabricated on single channel structures having the same channel strain. This difference has been attributed to additional midscale surface corrugations induced by the buried SiGe. This additional roughness had not been characterised separately from the large-scale crosshatch morphology commonly observed in SiGe SRBs. In this work, a surface roughness analysis technique has been developed to study the separate contribution from surface roughne~s components at different scales. It is shown that the addition,a. l midscale roughness induced by the buried compressive SiGe channel is fundamentally governed by the degree of compressive strain. Results correlate well with electrical data from devices fabricated on dual-channel structures. The use of supercritical strained Si channels is an alternative to improve hole mobility without incurring in additional midscale surface roughness introduced by compressive strain in the dual channel. Biaxially strained channels are commonly formed by growing Si on a strain-relaxed SiGe buffer (SRB). However, the device self-heating due to the low thermal conductivity of SiGe remains an obstacle to realising the full advantages of strained Si technology. Self-heating effects are further aggravated by the fact that SiGe buffers are typically several microns thick. Novel epitaxy techniques have enabled the production of ultrathin SRB in order to lessen the impact of selfheating. In this work, the material quality and stability of thin SRBs produced by two different growth techniques are investigated in terms of surface morphology and crystal defects. Both sub- and supercritical thickness layers are studied. Supercritical thickness layers have the potential to eliminate several challenges associated with processing SiGe, if material quality can be maintained. Also, improved hole mobility could be achieved in supercritical highly~strainedSi layers. The thermal stability of the thin SRB grown by a carbon-induced-relaxation technique is analysed by annealing the material at temperatures commonly used during device processing. Although strain measurements by Raman spectroscopy suggest good thermal resilience of this thin SRB, chemical defect etching demonstrates the evolution of dislocations, suggesting a weak thermal resilience. Supercritical strained Si layers growp on these thin SRBs exhibited prominent surface defects, most likely resulting·from additional strain-relief mechanisms in the thin SRB in addition to stacking faults. Defect etching techniques were developed in order to distinguish defect types from individual layers throughout the epitaxial layer stack. MOSFETs were also fabricated on thin SiGe buffers produced by a lowtemperature growth method and performance was compared with co-processed devices on a conventional thick SRB. The thin SRB devices exhibited reduced selfheating levels in comparison with conventional thick SRB devices. The lowtemperature growth technique leads to reduced surface roughness, which appears to improve key 'electrical parameters in addition to mobility, including gate leakage, reliability, noise and interface trap density. The impact of growth temperature on surface roughness and performance is also analysed.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available