This thesis proposes original methodologies for efficient implementation of complex signal processing algorithms in hardware. These will operate in the context of the TETRA Release 2 (TErrestrial Trunked RAdio) wireless communication standard; also known as TETRA Enhan~ed Data Service (TEDS). The aim of TETRA Release 2 is to add high-speed data communication capability to the established secure wireless TETRA standard. This will be achieved by utilizing: wider bandwidths; more sophisticated Quadrature Amplitude Modulation; channel coding as well as multi-carrier mdClulation. All this poses a serious challenge for implementation of low-power, cost-effective and high-performance mobile radio platforms. Several improvements have been made to the TETRA Release 2 base band signal processing algorithms. The improvements involve enhancing the performance and reducing the computational complexity of these algorithms. Including synchronization, multi-carrier demodulation, channel estimation and link adaptation. To meet the tight specifications of the standard, which is designed around non-optimal parameters, a novel harqware/software co-verification strategy is discussed to aid partitioning, verification, and analysis of the algorithms involved. A memory and area efficient implementation of a fully pipelined turbo-decoder is presented. This can achieve up to 58 Mbits/s decoding throughput by utilizing only a single Soft-In-Soft- Out (SISO) decoding unit. To address the demanding re-configurability requirement of the standard, a Partial Reconfiguration (PR) solution for TETRA Release 2 is presented. The proposed. solution can also be used in other wireless telecommunication standards. We believe this solution will appear in commercial applications in the near future and arguably, be the prime candidate for Software Defined Radio applications.