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Title: Methodology for generic architecture definition for current mode converters including automated building block characterisation and mismatch modelling
Author: Gevaert, Dorine
ISNI:       0000 0001 3495 4898
Awarding Body: Leeds Metropolitan University
Current Institution: Leeds Beckett University
Date of Award: 2007
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The challenges for the next generation of integrated circuit (IC) design of analogue and mixed-signal building blocks in standard CMOS technologies for moderate signal conversion in broadband applications, demand research progr~ss in the emerging scientific fields of device physics and modelling, converter architectures, correction algorithms, design automation, technology development, quality assurance and cost factor analysis. The contribution of this thesis to converter architectures is in new topological reusable bUilding blocks for analogue-to-digital (ADC) current converters and improved switching techniques for digital-to-ana.'tlgue (DAC) current converters. A generic compiler for the current folding and interpolating ADC and current steering DAC converter architectures, which take into account the fast technological CMOS changes in an automated down-link towards the basic building blocks, reduces the design time considerably. The new current converter architectures have been realized for 12-bit accuracy in standard CMOS technology. The generic compiler allows fast architectural exploration for other converter specification and the impact on the sizing of the transistors at basic building blocks level for a certain quality specification to be determined. The contributions to modelling, quality assurance and cost factor are the total new concepts in deriving design curves to reduce the design time and to reduce the total chip area of the current converters. For each new technology design curves for standardized transistor sizes for noise level, threshold voltage, I-V curves, overdrive voltage versus lambda and mismatch error modeling of the standard deviation of the drain current for the target operation condition, are automatically derived. For other transistor sizes the values are calculated in an automated procedure. These new design concepts reduce the over-sizing of the transistors, compared to the existing methods, with 15 to 20% for the same quality specification. Besides the reduction of the silicon cost also the design time cost is reduced considerably.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available