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Title: Device and circuit simulation of nanoscale double gate SOI transistors
Author: Lim, T. C.
ISNI:       0000 0001 3610 1696
Awarding Body: Queen's University Belfast
Current Institution: Queen's University Belfast
Date of Award: 2008
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This thesis addresses the design and application of a state-of-the-art nano-scaled Undoped-Thinned Body (UTE) Double Gate Silicon-On-Insulator (DGSOI) for digital and RF applications using TCAD. A novel structure ofooSOI, which focuses on the source/drain extension regions, has been proposed. The research covers the characterizations, optimisations and application of this nano-scaled ooSOI incorporating gate underlap concept by way ofanalytical investigations, numerical device simulations and circuit simulations. MixedMode simulator; a sub-module from ATLAS Silvaco' allows the effect of significant external parasitics in a nano-scaled device to be investigated in the circuit environment. Therefore, the impact of the source/drain engineering ofa nano-scaled ooSOI has been directly analysed in various circuit applications, such as 2-stage CMOS inverter for digital application and Operational Transconductance Amplifier (OTA) for RF application. . . For the digital application, the sensitivity and trend of the gate delay TD and lOljlOFF current ratio of the ooSOI have been established and have shown to be able to meet the IlRS roadrnap for 65nm node and below for three types oflogic applications (lIP, LOP, LSTP). Whilst the optimal performance ofooSOI in a digital circuit requires spacer length s - O.5Le;, ensuring off-eurrent meets the IlRS roadrnap whilst achievrng minimum TD, the optimised s for RF performance of a single device requires longer spacer s - La to andfAro''' When a RF circuit is considered employing several devices, such as OTA, an even longer s exceeding gate length has been shown to be beneficial in maximising Early voltage (Vw, hence intrinsic gain (AI-1_0T.J without comprornisingfT_OTA' The sensitivity of both dc and RF design to the lateral source/drain doping profile has been assessed and an optimal profJ.1e has been identified by its gradient at the gate edge. Value in the range of 3 - 5 nrnIdecade represents an optimised d of a typical ooSOI for both digital and RF performance. The effect ofparasitic resistances to RF performance has been reviewed. More rigorous expressions and fAro'' have been proposed to demonstrate that the effect of the contact resistance at the drain is more significant onfAro'' than the contact resistance at the source. The overall research has yield valuable insights into the potential performance of ooSOI in circuit applications.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available