Use this URL to cite or link to this record in EThOS: https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.479318
Title: Energy-efficient SOC design technology and methodology
Author: Flynn, David Walter
ISNI:       0000 0001 3471 5109
Awarding Body: Loughborough University
Current Institution: Loughborough University
Date of Award: 2007
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Abstract:
This thesis covers the portfolio of research projects addressing dynamic and static power reduction applicable to mass-market designs. It covers work over the period 2001-2006 while employed in the Research and Development Group at ARM Ltd in Cambridge, UK, and seconded during 2005 to ARM Inc. in Sunnyvale, California, USA. The Research Programme has been focussed on developing design styles and methodologies for synthesizable microprocessor and support Intellectual Property (IP) to address energy-efficient chip Implementation using both dynamic and static power reduction while minimizing changes required to tools and library components. A canonical System-On-Chip (SOC) design, representative of portable battery powered low-power customer designs, was specified and developed in the first year of the research project and has been extended and developed over the five years.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.479318  DOI: Not available
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