The success of the semiconductor industry relies on the continuous improvement of the performance of integrated circuits. This improvement is achieved by reducing the dimensions of the key component of these circuits: the metal-oxide-semiconductor field effect transistor (MOSFET). Indeed, the reduction of the device dimensions allows the integration of a higher number of transistors on a chip, enabling higher s peed, increased functionality and reduced cost. One of the key elements that allowed the successful scaling of the silicon-based MOSFETs is certainly the gate dielectric so far used in these devices, namely silicon dioxide. The superb material and electrical properties of silicon dioxide allowed the fabrication of properly working MOSFETs with silicon dioxide gate layers as thin as 1.5 nm. However further scaling down of the silicon dioxide gate layer thickness required for future CMOS (complementary metal-oxidesemiconductor) technologies, is problematic. Indeed, the leakage current density flowing through the transistors, arising from the direct tunneling of charge carriers exceeds 100A/cm', which lies well above the specifications given by the International Technology Roadmap for Semiconductors (ITRS). An alternative way of decreasing the silicon dioxide thickness in aggressively scaled MOSFETs is to use a gate insulator with a higher relative dielectric constant k than silicon dioxide. Therefore a physically thicker gate layer, yet with the same electrical thickness than sub-one nanometer silicon dioxide can be used. This could potentially reduce the leakage current of the gate dielectrics. In this respect, hafnium dioxide is considered as one of the most promising candidate for the 45 nm node due to its high dielectric constant (20 — 25), thermal stability on silicon, and sufficiently high values of conduction and valence band offsets with silicon. However, despite important success achieved in high - dielectrics, challenges must be overcomed before high - k dielectrics can be introduced into production. The major challenges are threshold voltage control for poly-Si electrodes, reliability issues, threshold voltage instability due to transient charge trapping, and low electron channel mobility. During this work, C apacitance-voltage (C-V), C apacitance-transient (C-2), Current-Voltage (/-V) evaluation techniques are used to investigate the properties of hafnium based gate dielectrics, In addition, the spectroellipsometry (SE) technique is used for assessing the optical properties of the high-k dielectrics and Photocurrent-voltage (Photo /-V) technique is used to evaluate oxide trap density and centroid. A full study of the properties of hafnium aluminates is detailed with a combination of a physical characterization technique (SE) and electrical assessment (C-V, J-V). The SE measurements show that the incorporation of aluminium into hafnium dioxide significantly improves the thermal stability of the oxide but at the cost of decreased dielectric constant. The electrical assessment shows the flat-band voltage and the relative dielectric constant can be adjusted when the aluminium concentration is varied. Evaluation of oxide trap concentration and centroid of trapped charge is investigated using Photo -V measurement. A novel technique based on pulsed MOS capacitor for studying the dynamic behaviour of charge trapping/de-trapping is introduced. This technique allows the measurement of oxide charging and discharging down to ~100 Ls with a relatively simple set-up. This technique is demonstrated and investigated in depth by applying to both the cases of charging and discharge of hafnium dioxide in a MOS system. The trap density obtained is compared with previously published data using different techniques.