Use this URL to cite or link to this record in EThOS:
Title: Low temperature seeded crystallization of amorphous silicon for transistor in grain technology
Author: Hakim, Mohammad Mojammel Al
ISNI:       0000 0001 3405 8663
Awarding Body: University of Southampton
Current Institution: University of Southampton
Date of Award: 2007
Availability of Full Text:
Access from EThOS:
Full text unavailable from EThOS. Please try the link below.
Access from Institution:
The continued scaling of MOSFETs to the deca-nanometre regime has reached the point where the transistor size is now comparable with the grain size in a polysilicon film (typically 100-200nm). The time is therefore right to research processing techniques that would allow a transistor to be fabricated inside a grain of polysilicon. Such transistors would be expected to have significantly better performance than thin film transistors (TFTs) because grain boundaries would be eliminated from the channel region. The transistor performance might also approach that achievable in single-crystal silicon if good control could be obtained over the quality of the silicon inside the polysilicon grain. The applications for transistor-in-a-grain technology would potentially be enormous, and would include high-performance large area electronics, displays and any technology where low temperature processing was required. In the longer term, this technology may also be attractive for post-scaling CMOS, since it would enable 3D CMOS technologies to be implemented. Layers of polycrystalline silicon self-assemble during growth and hence the positions of the grains and grain boundaries are random. The key issue in researching transistor-in-a-grain technology is therefore to devise processing techniques that allow the polysilicon grains to be precisely located with respect to the position of the transistor. This thesis investigates grain localization techniques and transistor architectures for transistor-in-grain technology. Two novel methods of low temperature crystallization of amorphous silicon are researched to increase the grain size and controlling the grain boundary locations. One method uses fluorine during metal induced lateral crystallization (MILC) of amorphous silicon. It is shown that fluorine implantation can be used to increase the lateral crystallization width during nickel-induced lateral crystallization of amorphous silicon at 500°C. The fluorine implant also gives an improved grain texture and a five times lower density of nickel-silicide precipitates in the laterally crystallized silicon. It is unambiguously shown that these effects are due to the suppression of random crystallization at the bottom interface by a chemical effect of fluorine. To devise a lateral crystallization technique that does not introduce metal contamination germanium induced lateral crystallization of amorphous silicon is also studied. A new α-Si crystallization phenomenon is identified which originates from the perimeter of a germanium layer during a low temperature anneal, giving a uniform lateral crystallization at a significantly lower thermal budget. The effect of amorphous Si thickness and doping on the perimeter crystallization are investigated. The perimeter crystallization is only observed in amorphous silicon films with thicknesses ≤ 100 nm, and the crystallization width increases with decreasing film thickness and increasing doping level. It is shown that the perimeter crystallization is due to the formation of large grains as a result of an increased growth rate of pre-existing grains and this is attributed to the strain generated by the thermal expansion of the germanium layer during anneal. Fabrication of single grain transistors in vertical pillars is a promising approach as completely single crystal silicon pillars can be realized by metal-induced crystallization of amorphous silicon. Hence, we simulate the electrical characteristics of very thin pillar vertical MOSFETs at pillar widths compatible with complete pillar crystallization. Floating body effects in vertical MOSFETs due to body isolation by the drain depletion region at the bottom of the pillar are investigated for pillar thicknesses in the range 200-10 nm. The transition from partial to fully depleted behavior is simulated and the impact of the body contact during this transition is described. For pillar thickness > 120 nm depletion isolation does not occur and hence the body contact is found to be completely effective, whereas for pillar thicknesses < 60 nm depletion isolation occurs for all drain biases and hence the body contact is ineffective. For intermediate pillar thicknesses of 60-120 nm, floating body effects are observed in the output characteristics due to partial depletion isolation. The relative contributions to the drain current of depletion isolation and gate-gate charge coupling are quantified and it is found that depletion isolation has a significant effect on the drain current down to a pillar thickness of 40 nm.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available