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Title: The formation of ultra-shallow p-type junctions using vacancy engineering
Author: Smith, Andy
Awarding Body: University of Surrey
Current Institution: University of Surrey
Date of Award: 2006
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For the last 40 years a natural demand for faster, more complex, and therefore, more functional electronic systems, has been the fundamental driving force behind the miniaturisation of the complementary metal oxide semiconductor transistor. The formation of highly conducting, ultra-shallow, p-type junctions is a key component for the source/drain contact and extension regions of the p-channel metal oxide semiconductor transistor. However, the requirements are becoming increasingly more difficult to achieve as technology advances. In fact, new ways of achieving device improvements are being considered. One method currently being implemented within industry is a switch from bulk silicon substrates to silicon on insulator (SOI). Therefore, it is important for any new techniques to be SOI compatible. The most commonly used p-type dopant, boron, suffers from process related phenomena which hinders the creation of such shallow junctions. During annealing interstitial defects remaining from the implantation process impede the junction formation through a defect-dopant interaction, which reduces the electrical activation and enhances the junction depth - the exact opposite to what is required! This thesis studies a technique which generates an excess of vacancy defects (a vacancy is essentially a missing silicon atom). The vacancies counteract the effect via an interstitial-vacancy recombination mechanism, thus reducing their detrimental effect on the subsequent boron implant. A detailed investigation into the optimisation of such a technique has been achieved through Monte Carlo simulations and experimental studies on diffusion, electrical activation and lattice damage in bulk silicon and SOI. It has been shown that it is possible to optimise the boron and vacancy generating implants to achieve a near "diffusionless" process, producing a junction depth of around 17nm, with an extremely high level of electrical activation (~5x1020cm-3) at low annealing temperatures. Furthermore, the junction is extremely thermally stable (600-900°C) giving rise to a large process window for ease of integration. Overall, this optimised technique rivals competing processes with a much lower equipment cost and "footprint" making it potentially a highly viable alternative to the current preferred methodology within industry.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available