Built In Self Test (BIST) offers an economical and effective solution to the problem of testing VLSI circuits for manufacturing defects. The testability insertion phase for BIST is normally after the logic synthesis and verification in VLSI design cycle. Most methods start from structural descriptions; they include testability features by re-arranging RTL descriptions in order to make the designs more testable. Such methods are sometimes called as high-level test synthesis. Considering testability at such a late stage in design flow often leads to problems such as exceeding chip area, inability to achieve the required throughput and degraded performance. Even though it can be argued that good results have been obtained with such approaches, we must keep in mind that, with the emergence of commercial behavioural synthesis tools, it is difficult for the designer to understand an automatically generated structural RTL description. With ever-increasing levels of complexity and an ever-shrinking time to market window, test synthesis must not be dissociated from design synthesis. High-level CAD tools allow designers to address testability concurrently with design at the highest level of abstraction, promoting the possibility of generating designs optimised both in terms of functionality and self-test. We show that by considering testability at the same time as other design parameters, a better overall solution can be obtained. This work shows that it is possible to generate optimised self-testable RTL from a behavioural description. This is achieved by developing novel and accurate incrementally iterative BIST resource estimation methods and integrating them within a unified synthesis flow. BIST resource estimation is done from the target architecture control path of the design behaviour during design space exploration. In the proposed integration for testability we exploit the available data flow graph information of the design for an automated generation of self test structures for the data path and controller pair.