As electronic systems become ever more complicated, so the requirement for complex interconnection between systems increases. This is true at all levels from the chip metallisation itself, through the first die-level packaging to the Printed Circuit tracks falls to the sub-micron level, current lithographic processes continue to confine these tracks to a 2֊dimensional surface on which space is becoming more and more of a premium. Some progress has been made to address this limitation by using three-dimensionally structured photolithographic masks, which are manufactured to mate as closely as possible with the surface on to which the image is to be projected. However, such an approach is intrinsically complex and limited to simple enclosure shapes that make the method practicable. In addition, it is difficult to achieve accurate alignment and the narrow line widths that will be required in future systems. Alternative approaches have used lasers to write directly on to a photolithographic material deposited on the surface of the structure. This method is very successful, but suffers from low throughput due to the need to scan the whole surface to be exposed. This thesis concerns the development of a novel lithographic method for the creation of electronic circuitry over non-planar surfaces and within volumes using Computer-Generated Holograms (CGH). The technique is developed in such a way as to allow the imaging onto a suitably prepared substrate of features whose size is of the same order as that used in the writing of the holographic mask, thus providing a comparative replacement to a standard photolithographic mask used in the production of PCBs and Integrated Circuits (ICs).