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Title: High frequency dividers in bulk and silicon-on-insulator CMOS technologies
Author: Mistry, Ketan
ISNI:       0000 0001 3411 1866
Awarding Body: University of Southampton
Current Institution: University of Southampton
Date of Award: 2005
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One of the key components common in integrated receiver designs is a RF local oscillator. This particular block is implemented as a phase-locked loop frequency synthesiser in many published high frequency architectures. A sub-block of this loop is the frequency divider, which sits in a feedback loop between the phase detector and voltage controlled oscillator (VCO). It is this block, along with the VCO, that operate at very high frequencies, and will therefore be heavy consumers of power compared with low frequency blocks. This thesis brings together the results of an investigation into frequency division, with a particular emphasis on high frequency dual-modulus dividers intended for fabrication in a CMOS process. The motivation behind this research is driven by the continuous demand for low power high speed circuits, as justified above. The static source-coupled logic forms the basis of the high frequency divider cells, and investigation into its behaviour and attempts to ascertain what restricts its high frequency characteristics. After a review of some published dividers, attention is turned to the phase selection architecture and a glitch-free control scheme that will play a key role in the design of two dual-modulus dividers. One such divider is the divide-by-64/65, which also demonstrates a new circuit topology in which stacking and current re-use exploit SOI CMOS technology. The second is a divide-by-16/17 circuit implemented in bulk sub-micron CMOS again with current-steering, but with the omission of stacking and thus makes for a useful comparison. This second divider also plays a crucial role in the design of a subsequent integer-N programmable divider (divisors 513-544), intended for use within a frequency synthesiser as part of a wireless IEEE802.11a complaint receiver IC, and it is detailed in the penultimate chapter. Another divider circuit developed in this work is a fixed divide-by-2 bulk CMOS cell capable of operating beyond 10GHz, intended for the very same wireless project. All divider circuits have been fabricated and successfully measured with results given in each of their individual discussions.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available