This thesis is concerned with the hardware implementation in VHDL (VHSIC Hardware Description Language) of a Generalised Minimum Distance (GMD) decoder for Reed Solomon (RS) codes. The generic GMD decoder has been implemented for the Reed Solomon codes over GF(28 ). It works for a number of RS codes: RS(255, 239), RS(255, 241), RS(255, 243), RS(255, 245), RS(255, 247), RS(255, 249), and RS(255, 251). As a comparison, a Hard Decision Decoder (HDD) using the Welch-Berlekamp algorithm for the same RS codes is also implemented. The designs were first implemented in MAT LAB. Then, the designs were written in VHDL and the target device was the AItera Field Programmable Gate Array (FPGA) Stratix EP 1 S25-B672C6. The GMD decoder achieved an internal clock speed of 66.29 MHz with RS(255, 251) down to 57.24 MHz with RS(255, 239). In the case of HDD, internal clock speeds were 112.01 MHz with RS(255, 251) down to 86.23 MHz with RS(255, 239). It is concluded that the GMD needs a lot of extra hardware compared to the HDD. The decoder GMD needs as little as 35% extra hardware in the case of RS(255, 251) decoder, but it needs 100% extra hardware for the RS(255, 241) decoder. If there is an option to choose the type of RS code to use, it is preferable to use the HDD decoder rather than the GMD decoder. In real world, the type of RS code to use is usually fixed by the standard regulation. Hence, one of the alternative way to enhance the decoding performance is by using the GMD decoder