Digital video technology has been characterised by continued growth in the last decade. The uses of video coding are broad and diverse. However, generally they fall into two main categories either utilising limited storage or transmission bandwidth. Video coding is essential for video on Digital Versatile Disc (DVD) and utilising the limited bandwidth available for realising real time applications such as videoconferencing, videotelephony and digital television. The use of Differential Pulse Code Modulation (DPCM) enables reduction of temporal redundancy between successive frames by frame differencing. The efficiency of this method is enhanced by motion compensating the predicted frame before differencing. The use of block motion estimation for the implementation of motion compensated video compression has become the favoured technique in video coding standards such as H.26-(l,3) and MPEG-(1,2,4). Motion estimation is the most demanding aspect of video coding. Motion estimation accounts for some 50% of the total computation needed in the H.261 video coding standard. The use of Very Large Scale Integration (VLSI) digital implementations enables this processing rate to be realised in real time, vital for communication purposes. Therefore power dissipation and implementation area of such implementations tend to be excessive. The research described in this work attempts to provide an efficient Complementary Metal Oxide Semiconductor (CMOS) integrated circuit realisation of the motion estimation processor based on analogue circuit techniques. The goal is to use compact analogue computation circuits in place of large digital arithmetic units with corresponding reduction of implementation area and power dissipation. These requirements are essential for battery operated video applications. It is hoped that the work presented in this thesis that explore and characterise the issues relating to the integrated circuit realisation of an analogue motion estimation processor, will provide the basis for future video coding standard implementations.