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Title: An investigation into the realisation and testing of a universal logic primitive gate array
Author: Zhang, Chengjin
ISNI:       0000 0001 3577 1217
Awarding Body: University of Bath
Current Institution: University of Bath
Date of Award: 1988
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No abstract available
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available
Keywords: Circuit logic gate arrays