Use this URL to cite or link to this record in EThOS:
Title: Cost modelling for VLSI circuit conversion to aid testability
Author: Miles, J. R.
ISNI:       0000 0001 3398 4083
Awarding Body: University of Brunel
Current Institution: Brunel University
Date of Award: 1988
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No abstract available
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available
Keywords: Programmable logic arrays