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Title: A general purpose parallel computer
Author: Rushton, Andrew John
ISNI:       0000 0001 3539 7691
Awarding Body: University of Southampton
Current Institution: University of Southampton
Date of Award: 1987
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The processor-array is a parallel computer consisting of an interconnected array of processors sharing a single controller. The controller is similar to that of a conventional computer, whilst the processors are usually kept simple. Consequently the processor-array is relatively easy to implement, making it an attractive parallel architecture. However, there are disadvantages to this approach which have tended to restrict the areas of application of the processor-array to those requiring only simple operations on very large arrays of data. This thesis describes a processor-array architecture with novel features that overcome these limitations. This architecture is called the Reconfigurable Processor-Array (RPA). It has the same advantages as a conventional processor array - a single controller and many identical, simple, processors - but it is a more general purpose architecture. The RPA can process arrays of data smaller than the array of processors, a flexibility achieved by allowing clusters of processors to operate on each element of data. The processors themselves have been improved to make them suitable for complex operations by the addition of specialised hardware. Particular emphasis has been placed on floating-point arithmetic, which is notoriously inefficient on the simple processors of processor-arrays. The implementation of a chip containing 16 identical processors for the RPA is described. An array can be built using just this processor chip and conventional RAM chips.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available
Keywords: Parallel computer networks