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Title: The use of selective epitaxy to prevent latchup in CMOS
Author: Sabine, Keith
ISNI:       0000 0001 3544 2202
Awarding Body: University of Southampton
Current Institution: University of Southampton
Date of Award: 1987
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CMOS is becoming the preferred technology for VLSI owing to its low power dissipation and high performance. However, scaled processes suffer from latchup, and the deep (3-4 micron) well used to avoid punchthrough limits packing density. In this work these problems are addressed and a novel method of well formation using selective epitaxial deposition in etched wells is proposed. Using this method, low well sheet resistance can be achieved and lateral well diffusion is minimised. A consideration of the mechanisms for selective epitaxial growth shows that deposition temperature must be low to achieve planar well surfaces. This is confirmed by experiment using the SiCl^/He/HCl system. Devices fabricated on uniformly doped epi require epi thicknesses greater than 3 microns to achieve 5V operation, in agreement with theory. Incorporation of a highly doped buried layer is shown to raise the punchthrough voltage over that of junction avalanche breakdown, and it is demonstrated that ~ 1 micron wells are feasible. PMOS transistors fabricated in shallow N wells by selective epitaxy show good characteristics and improved latchup immunity due to the low resistance buried layer. An increase of an order of magnitude of latchup holding current was achieved over devices fabricated in a conventional implanted well process. Latchup holding voltage of selective epi devices was 12V, indicating that latchup is not self-sustaining at normal supply voltages.
Supervisor: Chang, Benny Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available
Keywords: Semiconductor fabrication