Use this URL to cite or link to this record in EThOS:
Title: The development of an indium gallium arsenide junction field effect transistor for use in optical receivers
Author: Wake, D.
ISNI:       0000 0001 3550 7985
Awarding Body: University of Surrey
Current Institution: University of Surrey
Date of Award: 1987
Availability of Full Text:
Access from EThOS:
Access from Institution:
The objective of this work was to design and develop a high performance field effect transistor to be suitable for monolithic integration with a photodetector for use in long wavelength optical communication systems. It was decided that the most promising type of device for this application was a junction field effect transistor (JFET), fabricated using the alloy In.53Ga.47As grown epitaxially onto an InP substrate. The requirements for such a device were that it should have high transconductance, low input capacitance, and low gate leakage current (for high receiver sensitivity), and that it should have a structure which would be easily integrated monolithically with the desired type of photodetector - an In.53Ga.47As PIN-photodiode. Although this alloy semiconductor has favourable electron transport properties, at the start of this work, high performance field effect transistors had not been realised in this material. In particular, the In.53Ga.47AS FETs that had been made at that time were characterised by low transconductance. Using a device design that incorporated many novel and efficacious features, the JFET described in this work gave results which greatly surpassed all previous (and current) published results of similar devices. This device not only showed high performance, but the novel design features also enabled a simple fabrication scheme. Having developed this very high performance discrete device, the feasibility of monolithic integration with a In.53Ga.47As PIN-photodiode was demonstrated. Although the physical size and material requirements of these two devices were very different, novel design features enabled the construction of a monolithic PIN-FET combination, in which the performance of the JFET was not compromised.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available
Keywords: Integrated InGaAs/InP PIN-JFET