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Title: Failure mechanisms in MOS devices
Author: Amerasekera, Ekanayake A.
ISNI:       0000 0001 1633 2710
Awarding Body: Loughborough University of Technology
Current Institution: Loughborough University
Date of Award: 1986
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Continuous and pulsed voltage stressmg of metal oxide semiconductor (MOS) transistors and capacitors has been mvestigated. The expenmental work followed a survey of failure mechanisms in semiconductor devices which Identified Electrical Overstress Damage (EOS)/Electrostatic Discharge (ESD) damage as the most frequent cause of failure, accounting for over 50% of all damage observed. The survey itself, covered all aspects of semiconductor reliability including reliability modelling and quality assurance. A qualitative model of oxide breakdown in MOS structures was developed as a result of the experimental work. Two different mechanisms have been proposed for continuous and pulsed voltage breakdown. Continuous voltage breakdown simulating EOS conditions, was temperature and voltage dependent. The long time-scales involved, lead to a model whereby breakdown IS the result of conduction of charge earners through the oxide, via electron traps and impunty Sites with energies m the forbidden gap. Pulsed voltage breakdown simulating ESD, was voltage dependent but not temperature dependent. The very short time-scales involved indicate that breakdown is the direct result of electron transport m the oxide conduction band. Electrons are inJected into the conduction band via quantum-mecharucal tunnelling from the cathode. Both mechanisms were found to be dependent on the surface charge concentratiOn of the Silicon and, therefore, polanty dependent. The models explain this effect by analysing the charge injection process under high electric fields.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available
Keywords: Semiconductor device failure