Use this URL to cite or link to this record in EThOS: https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.369310
Title: Message routing interface for multiprocessor networks
Author: Ng, Jien-Hau
ISNI:       0000 0001 3444 9672
Awarding Body: Nottingham Trent University
Current Institution: Nottingham Trent University
Date of Award: 2001
Availability of Full Text:
Access from EThOS:
Full text unavailable from EThOS. Please try the link below.
Access from Institution:
Abstract:
Novel network interface hardware for interfacing PCs to a multiprocessor network based on multiple StrongARM processor nodes is presented in this thesis. The multiprocessor network, called SARNet, linked by packet routing switches, was designed for embedded distributed real-time control applications. Through the new interface hardware, PCs and the existing SARNet can be connected together to form heterogeneous networks. Initially, a general architecture of network interface hardware was investigated focussing on important issues affecting network interface designs. A review was also carried out on related areas including standard Input/Output (I/O) buses and parallel processing networks. From this, a prototype high-level interface model was produced. Using this, a theoretical analysis based on the model was conducted to estimate the performance of the network interface hardware and its subsystems. Appropriate technologies were selected in order to realise the novel network interface in hardware. VHDL, a hardware description language, was utilised for producing and simulating the network interface hardware. The hardware utilised a Peripheral Component Interconnect (PCI) bus standard for communication with the host PC. The interface was implemented in a single programmable logic device, to enable tight system integration, create flexibility for design modifications and allow the scope of design reuse. In addition, the hardware was optimised for communications between PCs and SARNet. Experiments were conducted to verify the functionality and measure the real performance of the hardware. The results obtained were compared against the theoretical estimations. The new interface hardware enables systems with different architectures to communicate via the specified standardised network interconnections. It reduced loading the host PC by using a bus-mastering technique for data transfers. The software load and complexity are reduced by incorporating hardware support for the data transmission protocol. In addition, the hardware enables continuous data flow between PCs and the SARNet.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.369310  DOI: Not available
Keywords: Parallel processing
Share: