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Title: SWAR systems and communications applications
Author: Spracklen, Lawrence A.
ISNI:       0000 0001 3475 5506
Awarding Body: University of Aberdeen
Current Institution: University of Aberdeen
Date of Award: 2001
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In recent years, the instruction sets of the majority of present day general purpose processors have been extended to include a variety of SWAR (SIMID Within A Register) instructions. These operations, which make possible the processing of multiple data elements with a single instruction, have been proven to facilitate the acceleration of a wide range of graphics and multimedia applications. The application of these instructions is not, however, just limited to this type of program, and current research is concerned with developing high performance implementations of a wide range of new applications. The initial part of this thesis presents a number of innovative strategies for accelerating previously un-addressed classes of application and illustrates that a significant degree of acceleration can frequently be achieved. However, for all of the applications analysed, several SWAR specific problems were repeatedly encountered. For the efficient operation of the implementation developed using these SWAR instructions, the organisation of the data to be processed is of critical importance and the required arrangement frequently fails to match that normally encountered in applications. SWAR ISEs (Instruction Set Extensions) usually contain functionality to address these problems, but it is shown by the author that this current functionality is insufficient and significantly curtails the performance achievable with these ISEs. The VMM (VIS Manipulation Matrix) was developed to address this problem and provide a methodology whereby the performance obtained using SWAR methodologies could be made significantly more independent of the underlying data organisation. The functionality of the VMM is presented and the effectiveness of this methodology is highlighted, by considering its application to a number of important algorithms. Finally, the feasibility of integrating the VMM into a general purpose processor is revealed, by highlighting its compatibility with the UltraSPARC processor.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available
Keywords: SIMD; Register