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Title: Some aspects of submicron CMOS technology
Author: Afshar-Hanaii, Nasser
ISNI:       0000 0001 3399 0475
Awarding Body: University of Southampton
Current Institution: University of Southampton
Date of Award: 1993
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Scaled submicron devices require shallow source and drain junctions and thin and reliable gate dielectrics for the alleviation of short-channel and hot-carrier effects. MOSFETs with elevated sources and drains can provide shallow junctions without increasing the sheet resistivity of the n⁺ and p⁺ layers and also prevent aluminium from spiking through the junctions. Nitrided oxides and re-oxidized nitrided oxides prepared by rapid thermal annealing can provide thin gate dielectrics which are more hot-carrier resistant than pure oxides. This thesis reports on work that has been carried out by the author for the development of a twin-well CMOS technology for the fabrication of submicron MOSFETs. A selective epitaxial growth (SEG) of silicon process has been developed using a low-pressure CVD reactor to produce SEG films required for the fabrication of MOSFETs with elevated sources and drains. For the first time, thick layers of SEG films of up to about 1μm have been grown in a pure SiH_4 system at 960^oC. The quality of the SEG films was assessed by C-t measurements and TEM observations and found to be single crystalline silicon. The minority carrier life-time in the films was found to be two orders of magnitude lower than the best quality epitaxial films, yet more than 200 times higher than that of the large grain polycrystalline silicon. An excellent uniformity (±5% and reproducibility was achieved for this process. The SEG films grown in the low-pressure SiH₄ system were used for the fabrication of submicron n- and p-channel MOSFETs with elevated sources and drains. The CMOS devices showed comparable characteristics to those of the transistors fabricated in a standard twin-well CMOS process with the same parameters. However, short-channel effects (DIBL) were greatly reduced for the elevated S/D structures (~2.8x reduction in punchthrough current at V_GT= 0V).
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available
Keywords: Dielectrics