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Title: A fast Fourier Transform accelerator for a transputer system
Author: Dodge, Christopher J.
ISNI:       0000 0001 3427 0437
Awarding Body: University of Aberdeen
Current Institution: University of Aberdeen
Date of Award: 1993
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Multiple Instruction, Multiple Data (MIMD) networks can produce scalable processing power for a wide variety of image computing applications. For certain tasks however, data-distribution bottlenecks reduce the maximum achievable performance gain. Digital Signal Processing (DSP) technology is capable of high performance from a single processor, thus avoiding some of the data communication problems associated with multi-processor systems. Nevertheless, many practical applications require the incorporation of processing primitives provided by single computational elements, such as DSP, within a more general computational domain. The Fast Fourier Transform (FT) is typical of a class of algorithm frequently used in image processing that can be computed by a single DSP processor in the same time interval as a system containing many MIMD processors. The work investigates the design, construction and properties of a hierarchical computing system, capable of implementing complete FT transforms on two dimensional data structures. The basic hardware comprises a proprietary DSP processor, a controlling transputer and multiple, switched, banks of fast static random access memory (SRAM). The design strategy successfully allows the arithmetic operations of the DSP processor to be concurrent with the data exchange and input/output activities of the controlling transputer. The complexity of the resulting system prompted an investigation into structured design techniques. As the normal specification language Z has been shown to be a useful tool for software system design and documentation, its value in the design of a hardware system is explored. The way in which Z is utilised differs from existing applications to software system development, especially in the method of refinement towards a combined system of hardware, programmable logic and control software. After extensive design, construction and testing phases, initial validation shows that while the accelerator is a very powerful resource, capable of a complete 1024 point, one dimensional FFT in 560s, an efficiency of 45&'37 is difficult to exceed when repeated transforms are calculated.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available
Keywords: Computer hardware