This thesis is concerned with the design and analysis of bipolar preamplifier circuits suitable for use in optical communications receivers. The factors limiting speed of operation, sensitivity, and dynamic range are examined. One of the objectives of this work is to fully explore the potentiality of common-collector input designs. This type of input has previously been regarded as inferior to the common-emitter and cascode front ends, because the input-equivalent noise-current generator contains a high-level component due to the second stage shot noise. It is shown, however, that with a transimpedance design the second stage shot noise is generally of secondary importance. In addition, the-author has derived an original expr_essio. n for the second stage collector current, which reduces the second stage shot noise contribution to 'a minimum. Computer predicted results are presented for three common-emitter input, and four original common-collector input designs. Computer predicted results are also given for two common-collector designs using polysilicon emitter transistors. Experimental results are given for two discrete-component, p. c. b. built designs, (operating at 140 and 650 Mbit/s) and three, I. C. preamplifier based receivers operating at 140/320/565 Mbit/s. It is demonstrated that very high speed receivers can only be produced if transistors with low values of base-spreading resistance are employed.