Use this URL to cite or link to this record in EThOS:
Title: Formal specification and analysis of digital hardware circuits in LOTOS.
Author: He, Ji.
ISNI:       0000 0001 3550 1508
Awarding Body: University of Stirling
Current Institution: University of Stirling
Date of Award: 2000
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No abstract available
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available
Keywords: Language of Temporal Ordering Specification