Use this URL to cite or link to this record in EThOS: https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.320725
Title: The mathematical modelling of electrical and thermal acceleration factors in VLSI conductors
Author: Méjasson, Patrick Gérard
ISNI:       0000 0001 3392 4742
Awarding Body: University of Glamorgan
Current Institution: University of South Wales
Date of Award: 1996
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Abstract:
All semiconductor devices need electrical accessibility and thus some form of metal contact is required. This contact may be rectifying or ohmic, but the metals used in the chip construction are often unsuitable for making connections to the outside world. Invariably, layered metallizations are used to make the top metallic layer suitable for wire or tape ultrasonic-thermocompression bonding, usually involving aluminium or gold, or soldering using lead-tin alloys. When a semiconductor device is fabricated, it goes through a number of processes at the end of which it is metallized, passivated, encapsulated, and packaged, or any combination of these. The device engineer knows the structure of the device which will include a number of semiconductor-metal, insulator-metal, and metal-metal interfaces. In order to ascertain the operational reliability of the device, accelerated life-tests and predelivery burn-in or screening (or both) based on life tests are often carried out. This stressing involves operating the device either at high temperatures or at high current densities in normal atmospheric, corrosive or highly irradiated environments, or in environments consisting of combinations of these. The different interfaces in the device may change their characteristics through materials transferred by various means at the different stages mentioned above. The interfacial changes and any resultant alterations in the bulk of the constituting materials invariably alters the electrical or mechanical performances (or both) of the device which is said to have degraded. More importantly, operation of the device at high power levels or at high stressing causes thermal runaway and device failure. The work carried out and described in this thesis focuses on failures which occur in the connective paths, known as lines between individual device internal transistors. Firstly, the operation of the VLSI device in adverse elevated thermal and elevated current density conditions will be described. Whilst the process failure mechanisms under these conditions are well documented and mathematically defined, a new technique involving mechanical stress modelling has been developed to predict failures locations in the Al-Si 1% lines. Secondly, a new procedure has been developed to artificially 'age' VLSI devices in order to observe any degradation which may occur in the connecting paths. Several factors have been identified which can contribute to line degradation. These are high current density, high temperature and high mechanical stress. These factors together give rise to electromigration, resulting in the physical movement of line material, which eventually results in catastrophic line failure. It has been previously thought that only temperature and current density were the controlling factors, but this investigation has shown that mechanical stress has a major influence. A new model to predict electromigration phenomena locations in conductive paths has thus been developed based on mechanical stress, in addition to current density and surrounding temperature.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.320725  DOI: Not available
Keywords: Semiconductor devices
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