Use this URL to cite or link to this record in EThOS: https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.308795
Title: Asynchronous VLSI design
Author: Nedelchev, Ivailo Marinov
ISNI:       0000 0001 3440 4896
Awarding Body: University of Surrey
Current Institution: University of Surrey
Date of Award: 1995
Availability of Full Text:
Access from EThOS:
Access from Institution:
Abstract:
This thesis describes the background and implementation of a novel silicon compiler from a high-level programming language, OCCAM(async), to asynchronous CMOS circuits. The compilation scheme is based on a process algebra description of a concurrent system. This Algebra is called Delay-Insensitive Algebra and is based on CSP but allows the user more freedom in communication protocols. The thesis reviews and compares various, existing, design styles and their practical aspects for asynchronous design are also discussed. The syntax and the operational semantics of OCCAM(async) are defined and, on this basis, the new compilation technique is described with its underlying CMOS circuitry. The implementations of various, novel, library cells are also discussed. The compilation technique is illustrated throughout the thesis with practical examples. It is also compared to an existing synthesis tool, Tangram, which has been developed at Phillips Research Laboratories. The thesis concludes with the place and the role of OCCAM(async) in the contemporary CMOS design, and the future aspects in continuing this research into the full, design-process automation.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.308795  DOI: Not available
Keywords: Computer software & programming
Share: