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Title: Fault tolerance in distributed real-time computer systems.
Author: Baba, Mohd Dani
ISNI:       0000 0004 2752 1156
Awarding Body: University of Sussex
Current Institution: University of Sussex
Date of Award: 1996
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A distributed real-time computer system consists of several processing nodes interconnected by communication channels. In a safety critical application, the real-time system should maintain timely and dependable services despite component failures or transient overloads due to changes in application environment. When a component fails or an overload occurs, the hard real-time tasks may miss their timing constraints, and it is desired that the system to degrade in a graceful, predictable manner. The approach adopted to the problem in this thesis is by integrating the resource scheduling with fault tolerance mechanism. This thesis provides a basis for the modelling and design of an adaptive fault tolerant distributed real-time computer system. The main issue is to determine a priori the worst case timing response of the given hard realtime tasks. In this thesis the worst case timing response of the given hard real-time task of the distributed system using the Controller Area Network (CAN) communication protocol is evaluated as to whether they can satisfy their timing deadlines. In a hard real-time system, the task scheduling is the most critical problem since the scheduling strategy ensures that tasks meet their deadlines. In this thesis several fixed priority scheduling schemes are evaluated to select the most efficient scheduler in terms of the bus utilisation and access time. Static scheduling is used as it can be considered to be most appropriate for safety critical applications since the schedulability can easily be verified. Furthermore for a typical industrial application, the hard real-time system has to be adaptable to accommodate changes in the system or application requirements. This .goal of flexibility can be achieved by integrating the static scheduler using an imprecise computation technique with the fault tolerant mechanism which uses active redundant components.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available
Keywords: Computer hardware