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Title: Studies of propagation delay for high-speed bipolar logic circuits
Author: Fang, Wen
ISNI:       0000 0001 3457 0480
Awarding Body: University of Southampton
Current Institution: University of Southampton
Date of Award: 1990
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In order to optimise the performance of high-speed bipolar logic circuits, one would like to have an analytical expression that explicitly relates the propagation delay of a circuit to its electrical parameters. Such an expression provides a better insight into the relationship between the propagation delay of a circuit and its electrical parameters, and therefore it is very useful in design, optimisation and performance prediction of high-speed bipolar logic circuits. A linearity study of the propagation delay was carried out by using a SPICE circuit analysis program. It is found that the behaviour of the propagation delay is quite linear over a wide electrical parameter range and hence the propagation delay expressions for ECL, CML and XOR circuits are derived by means of the sensitivity analysis. The validity of these expressions are carefully checked over a wide range of transistor and circuit parameters by comparison with SPICE simulations and reported experimental data in the literature. With advances in gigabit per second communication systems, the need for very high-speed frequency dividers has become more important. A novel method was used to analyse frequency dividers by relating their performances to that of constituent XOR gates. Therefore, the XOR propagation delay expression is used to accurately predict the maximum toggle frequency of frequency dividers. Figures of merit have been derived for silicon and AlGaAs/GaAs HBT circuits. These expressions show that there is an optimum value of the load resistance (or the collector current density) for bipolar circuits in order to achieve a minimum propagation delay. By comparing the predicted optimum collector current densities with the current densities of maximum fT, it is found that increasing the current density of maximum fT is very important for silicon transistors, while reductions in τF, RB and RE are desirable for AlGaAs/GaAs transistors. The signal propagation delay due to large interconnect and off-chip output capacitances is a major factor determining the speed of VLSI circuits. In view of the driving capability of bipolar transistors, a BiCMOS buffer is usually adopted to drive the heavy capacitive load. An accurate BiCMOS delay expression is derived and influence of device parameters on BiCMOS circuit speed discussed. In order to predict the future performance of BiCMOS circuits, figure of merit is derived from the BiCMOS delay expression. Using the expression, it is predicted that future CMOS circuits can operate faster than BiCMOS circuits under the internal logic circuit assumption, while BiCMOS circuits can keep the speed advantage over CMOS circuits down to submicron dimensions under the constant load capacitance assumption.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available
Keywords: Bipolar VLSI circuits