Use this URL to cite or link to this record in EThOS:
Title: The computer aided design of combinational and synchronous logic systems
Author: Fox, Andrew
Awarding Body: University of Aberdeen
Current Institution: University of Aberdeen
Date of Award: 1989
Availability of Full Text:
Access from EThOS:
Full text unavailable from EThOS. Please try the link below.
Access from Institution:
A significant portion of a modern digital system can be regarded as a network of many thousands of combinational logic functions. In a Very Large Scale Integration (VLSI) implementation each combinational logic function is realized as a logic gate on a silicon wafer. To synchronize the passage of a signal through a network of logic gates synchronizing elements are used. These inhibit or permit the flow of a signal through the network under the control of a global control signal. A portion of a digital system comprising a network of logic gates connected without feedback is referred to as a combinational logic network. A portion of a digital system containing both combinational logic functions and synchronizing elements is referred to as a synchronous logic network. This thesis is concerned with the development of techniques and theory for the computer aided design of combinational and synchronous logic networks including techniques for: organizing a combinational logic function for a dynamic logic macrocell style of VLSI implementation; rearranging synchronous logic networks with the goal of improving the performance of a VLSI realization and synthesizing logic expression representations of designs from recursive equations in a correctness preserving way. In particular, the following methods for assisting with the design of logic systems are presented: 1. A method for factoring logic equations which allows constraints specific to a dynamic logic macrocell implementation to guide the search for the factored form. 2. A method for retiming multiple phase synchronous logic networks. 3. A method for reorganizing the distribution of logic in a synchronous logic network so that the delay encountered by a signal rippling through the combinational logic between any pair of synchronizing elements is reduced. Particular results obtained from implementations of the methods proposed demonstrate their usefulness for the computer aided design of logic systems.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available
Keywords: Computer-Aided Design