Strained SiGe heterostructures possess transport properties superior to Si. Their integration in the channel of MOSFETs can lead to an enhanced speed performance and is therefore an alternative to the scaling of the channel length. This thesis reports on the fabrication and characterization of p-MOSFETs with a strained SiGe channel. As both design and material properties determine the performance of MOSFETs, the mobility in the SiGe heterostructure must be seen in context with the MOSFET design. SiGe heterostructures fabricated by molecular beam (MBE) and solid phase (SPE) epitaxial growth have been successfully integrated in the channel of p-MOSFETs. A manufacturable SiGe CMOS process based on SPE has been demonstrated. A slightly enhanced oxidation rate and an increased interface state density have been observed for Si oxidized after Ge⁺ implantation. The low performance of the SiGe p-MOSFETs is explained by the scattering and-trapping of carriers at the degraded interface. This suggests that changing the annealing conditions could improve the SiGe p-MOSFETs. Devices have been fabricated on a locally grown MBE layer. A considerable mobility enhancement over Si references has been shown for devices with a SiGe layer grown by MBE - more than or nearly a factor of two for devices with an LTO or thermal gate oxide, respectively. The devices fabricated on pillars display considerably better transport properties than the devices not fabricated on pillars. Altering the standard cleaning procedures has enabled us to achieve the required process control of one nanometer. Otherwise, the carriers would not be confined in the buried SiGe channel and would not profit from its enhanced transport properties. Low source and drain resistances have been obtained for SiGe p-MOSFETs subject to a maximum processing temperature of 800°C.