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Title: Reconfigurable FPGA-based message routing for embedded real-time parallel processing applications
Author: Frost, Graham
ISNI:       0000 0001 3484 7363
Awarding Body: University of Surrey
Current Institution: University of Surrey
Date of Award: 1998
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To meet the requirements of high performance embedded applications, this thesis proposes an architecture in which multiple general-purpose processors are connected through a communication network to form a parallel processing system. Two aspects of this approach are considered. A network for connecting multiple processors must provide high speed, low latency communication to ensure that inter-processor communications do not degrade the overall computation performance. A proposal to use programmable-logic-based message routing nodes to construct such a network is investigated and the advantages of this approach are explored. A network design, produced using the hardware description language VHDL, is described and its verification by simulation is presented. Routing mechanisms incorporated in the design to improve network utilisation include multicast, adaption and encapsulation. The construction of a small network and its verification using four processors to generate messages and verify message delivery is described. The successful use of programmable logic provides a foundation for developing networks in which the specific router design is based on matching the resources of the network to those required by the application using a library of routing functions. An investigation into the processing requirements of a system which uses video cameras on a railway carriage to measure the relative position of station platforms and the rails is presented. The implementation of two algorithms to provide the platform position in real-time is investigated, and the generation of a database of real sensor data for further off-line algorithm development is described. The results obtained show that the requirements of the video measurement application can be met with a reasonable number of processors, and provide a metric for estimating the processor requirements of future systems. A new technique is presented which uses image processing to calibrate the video cameras so that optical alignment of the cameras is no longer critical.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available
Keywords: Computer software & programming