Use this URL to cite or link to this record in EThOS: https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.236904
Title: Finite state machine representation of digital signal processing systems
Author: Albinson, Lawrence J.
ISNI:       0000 0001 3410 0518
Awarding Body: University of Cambridge
Current Institution: University of Cambridge
Date of Award: 1981
Availability of Full Text:
Access from EThOS:
Full text unavailable from EThOS. Please try the link below.
Access from Institution:
Abstract:
A new method for implementing digital filters is discussed. The met11od maximises the output signal to noise ratio of a filter by assigning at each of the filter variables an optimal quantization law. A filter optimised for a gaussian process is considered in detail. An error model is developed and applied to first and second order canonic form filter sections. Comparisons are drawn between the gaussian optimised filter and the equivalent fixed point arithmetic filter. The performance of gaussian optimised filters under sinusoidal input signal conditions is considered ; it is found that the gaussian optimised filter exhibits a lower approximation error than the equivalent fixed point arithmetic filter. It is shown that when high order filters are implemented as a cascade of second order sections - with if necessary one first order section - the section ordering has a very small effect on the overall signal to noise r atio performance. A similar result for the pairing of poles and zeroes is found. Bounds on the maximum limit cycle amplitude for first and second order all-pole sections are presented. It is shown that for a first order all-pole the maximum limit cycle amplitude is lower than would be expected in the equivalent fixed point arithmetic filter, whereas , for the second order all- pole the bound is twice as large. Examples of a low-pass , band-pass and wideband differentiating filter,designed using free quantization law techniques,are presented. This new design method leads to a filter whose arithmetic operations can not be performed using fixed point arithmetic hardware. Instead, the filter must be represented as a finite state machine and then implemented using sequential logic circuit synthesis techniques. The logic complexity is found to depend - amongst other considerations - on the so called state (code) assignment. Some preliminary results on this problem are presented for the case of a next state function computed using the AND/EXCLUSIVE- OR (ring-sum) logic expansion. A review of the state assignment techniques in the literature is included. A part of the state assignment problem - for the case of AND/EX'·/OR logic - requires the numerous and consequently rapid computation of the Reed-Muller Transformation. A hardware processor - designed as an add-on to a minicomputer - is described; speed comparisons are drawn with the equivalent software algorithm.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.236904  DOI:
Share: