Use this URL to cite or link to this record in EThOS: https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.234003
Title: Fast packet switching for integrated services
Author: Newman, P.
ISNI:       0000 0001 3443 936X
Awarding Body: University of Cambridge
Current Institution: University of Cambridge
Date of Award: 1988
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Abstract:
As the communications industry continues to expand, two current trends are becoming apparent: the desire to support an increasing diversity of communications services, (voice, video, image, text, etc.), and the consequent requirement for increased network capacity to handle the expected growth in such multi-service traffic. This dissertation describes the design, performance and implementation of a high capacity switch which uses fast packet switching to offer the integrated support of mulit-service traffic. Applications for this switch are considered within the public network, in the emerging metropolitan area network and within local area networks. The Cambridge Fast Packet Switch is based upon a non-buffered, multi-path switch fabric with packet buffers situated at the input ports of the switch. This results in a very simple implementation suitable for construction in current gate array technology. A simulation study of the throughput at saturation of the switch is first presented to select the most appropriate switch parameters. Then follows an investigation of the switch performance for multi-service traffic. It is shown, for example, that for an implementation in current CMOS technology, operating at 50 MHz, switches with a total traffic capacity of up to 150 Gbit/sec may be constructed. Furthermore, if the high priority traffic load is limited on each input port to a maximum of 80% of switch port saturation, then a maximum delay across the switch of the order of 100 μsecs may be guaranteed, for 90% of the high priority traffic, regardless of the lower priority traffic load. An investigation of the implementation of the switch by the construction of the two fundamental components of the design in 3 μm HCMOS gate arrays is presented and close agreement is demonstrated between the performance of the hardware implementation and the simulation model. It is concluded that the most likely area of application of this design is as a high capacity multi-service local area network or in the interconnection of such networks.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.234003  DOI: Not available
Keywords: Switching techniques for LANs
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