Design verification is an essential step in the production of a custom integrated circuit because of the human involvement in the design process. In the early days of the microelectronics industry, the mask artwork would have been checked by visual inspection. Today, manual verification is itself too error prone because of the volume and complexity of the design data. This thesis describes the design of a programmable mask analysis system to check technology rules and extract circuits in a low cost computing environment. The System is programmed by means of a high level mask verification language (MVL) and can be adapted for use with a wide range of evolving process technologies. The MVL is designed to minimise the amount of procedural detail supplied by the programmer. The types of device for a given technology are described, in MVL, using tree shaped graphs. Each device description is accompanied by a short PASCAL-like procedure which determines how a device matching the description will be processed. Thus, the MVL programmer is only concerned with how a device is processed and not with how the device is actually recognised. The System includes an optimising MVL compiler which removes redundant mask operations, and efficiency is maximised by minimising the volume of mask data that must be processed. A modified scanline algorithm is used for geometry processing which, in a single sweep of the plane, performs the necessary operations on the mask artwork. The result of geometry processing is a set of topologically interrelated entities called features. These features are analysed to recognise devices using a goal oriented subgraph isomorphism algorithm and, for every device recognised, the appropriate MVL procedure is executed. The System has been used on NMOS, CMOS and I²L mask designs. The execution time has been found to be almost linearly related to the volume of input mask data, and the workspace required is proportional to the square root of the volume of the data.