Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.706578
Title: High-κ dielectrics on germanium for future high performance CMOS technology
Author: Wang, Zhong
ISNI:       0000 0004 6057 855X
Awarding Body: University of Liverpool
Current Institution: University of Liverpool
Date of Award: 2015
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Abstract:
Traditional silicon CMOS scaling has approached its limits due to the high leakage current induced by the reduction of the silicon-dioxide gate oxide thickness. Thus, high permittivity dielectric is suggested to replace SiO2 to achieve low gate leakage current while maintaining the same capacitance. Moreover, high mobility materials are being considered to replace Si as channel materials motivated by the requirement for higher drive current and faster switching speed of MOSFETs. Germanium (Ge) has attracted much attention as a channel material, attributed to its high hole and electron mobility. Overall, it could be concluded that a high-κ dielectric for the Ge gate stack could be an effective solution for future CMOS technology which could resolve these two concerns. However, surface passivation between the material high-κ and the Ge channel is a major challenge for this solution. Direct deposition of a high-κ dielectric on Ge suffers from a low-quality interface. The native oxide, GeO2 has been found to form a good interfacial layer on Ge before the deposition of a high-κ dielectric. Two methods are introduced in this work, to passivate the interface. Electrical and XPS characterization is employed to investigate the property of the interface. Several admittance behavior issues related to Ge-based MOS capacitor could lead to errors in the extraction of the interface state density using the conventional C-V or G-V based methods. The availability and scope of these methods are studied in details when applied on the Gebased MOS capacitor. Three issues related to the conductance method as a preferable method are explored. A conduction band notch which represents a potential charge trapping site may exist at the interface between the interfacial native GeO2 and high-κ dielectric layer in a Ge MOSFET gate stack. It could induce threshold voltage instability. The number of electrons and its induced threshold voltage is calculated and the main conclusion is that charge storage in this notch is insignificant at the relevant technology node. The low frequency response of the capacitance voltage characteristic is observed for the Gebased MOS capacitor in the inversion region, even at high frequency. It is considered to be the result of the fast minority carrier generation response. The extraction of activation energies through temperature measurement indicates that the thermal generation process is responsible for the generation of minority carriers at room temperature. The minority carrier generation life time is measured to model the thermal generation in the depletion region for Ge-based MOS. The frequency dispersion apparent in the accumulation regime of C-V plots for Gebased MOS is considered to be caused by oxide traps within the oxide layer. A model is employed to estimate the oxide trap concentration. It is demonstrated that the oxide traps are distributed non-uniformly over both oxide depth and energy level.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.706578  DOI: Not available
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