Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.702814
Title: New processing techniques for large-area electronics
Author: Yoon, Minho
ISNI:       0000 0004 6059 244X
Awarding Body: Imperial College London
Current Institution: Imperial College London
Date of Award: 2016
Availability of Full Text:
Access from EThOS:
Full text unavailable from EThOS. Please try the link below.
Access from Institution:
Abstract:
Recent advancements in the semiconductor industry have been driven by the extreme downscaling of device dimensions enabled by innovative photolithography methods. However, such nano-scale patterning technologies are impractical for large-area electronics primarily due to extremely high cost and incompatibility with large-area processing. Therefore, alternative techniques that are simpler, more scalable and compatible with large-area manufacturing are required. This thesis explores the technological potential of two recently developed patterning techniques namely interlayer lithography (IL) and adhesion-lithography (a-Lith) for application in the field of large-area nano/electronics. The IL method relies on the use of a pre-patterned metal electrode that acts as the mask during back illumination of a photoresist layer followed by a conventional lift-off process step. On the other hand in the a-Lith approach, the surface energy of a patterned metal electrode is modified through the use of surface energy modifiers such as organic self-assembling monolayer (SAM). Following, a second metal is evaporated on the entire substrate. However, because of the present of the SAM, regions of metal-2 overlapping with metal-1 can easily be peeled off with the aid of an adhesive layer (e.g. sticky tape) leaving behind the two metal electrodes in close proximity to each other. Analysis of the resulting structures reveals that inter-electrode distances < 20 nm can easily be achieved. The method was then used to develop innovative process protocols for the fabrication of functional self-aligned gate (SAG) transistor architectures. Best performing devices exhibited charge carrier mobility in the range of 0.5-1 cm2/Vs, high current on-off ratio (~104), negligible operating hysteresis and excellent switching speed. Using the same a-Lith process protocol, low-voltage organic ferroelectric tunnel junction memory devices were also developed by combining the metal-1/metal-2 nanogap electrodes with a ferroelectric copolymer deposited in-between them. Controllable ferroelectric tunnelling was observed enabling the devices’ conductivity to be programmed using low biases and hence been used as a non-volatile memory cell. The alternative and highly scalable patterning methods described in this thesis may one day play a significant role on how largearea electronics of the future would be manufactured.
Supervisor: Anthopoulos, Thomas Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.702814  DOI: Not available
Share: